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KS0035 53 segment static driver introduction the KS0035 is a general purpose lcd driving ic, and designed to be available for electronic frequency tuning display applications or microcomputer application systems. features . maximum 53 segment output for static display. . drive system : 1/1 duty r 53 segments 1/2 duty r 104 segments. . 3 input pins for serial data transfer ( ce , ck , di ) . 2 pins for 5 - level - ad converter ( ari , ali) . 2 display pins for direct displaying ( dsp1 , dsp2 ) . inh pin for blinking out display. block diagram * s44 ( dsp2 ) * s46 ( dsp1 ) * s48 ( dsp out ) * s49 ~ s53 ( arlo1 ~ arlo5 ) latch segment driver ( 1 ~ 56 bits ) latch segment driver ( 57 ~ 112 bits ) com1 com2 s1 s53 adc adc s47 ( ari ) s45 (ali ) shift register (56 bits ) function decoder di ck ce v ss v dd inh osc clock generator common driver v lcd s52 s51 s50 s49 s48 s46 s43 s44
KS0035 53 segment static driver pad diagram * there is mark of KS0035 on the center in chip. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 s48 s49 s50 s51 s52 s53 osc v dd inh v lcd v ss ce ck di com2 com1 s32 s33 s34 s35 s36 s37 s38 s39 s40 s41 s42 s43 s44 s45 s46 s47 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 KS0035 (0,0) x y chip size : 2380 ? 2980 pad size : 99 ? 99 pad pitch : 125 unit : m m
KS0035 53 segment static driver pad location pad name pad name pad number pad number coordinate coordinate y x y x 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 1265 940 815 690 565 440 315 190 65 -60 -185 -310 -435 -560 -685 -810 -935 885 760 635 510 385 260 135 10 -115 -240 -365 -490 -615 -740 -865 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 -965 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 s33 s34 s35 s36 s37 s38 s39 s40 s41 s42 s43 s44 s45 s46 s47 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -1265 -970 -845 -720 -595 -470 -345 -220 -95 30 155 280 405 530 655 780 905 -960 -835 -710 -585 -460 -335 -140 -15 110 235 360 485 610 735 860 985 965 965 965 965 965 965 965 965 965 965 965 965 965 965 965 965 s48 s49 s50 s51 s52 s53 osc v dd /inh v lcd v ss ce ck di com2 com1 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 unit( m m)
KS0035 53 segment static driver pad description pad input/output name description interface v dd operating voltage for logic circuit (2.7v~6.5v) v ss power 0v (gnd) power supply v lcd driver supply voltage power supply for driving lcd com1, com2 output common output - 1/1duty: only com1 is used, com2 open - 1/2duty: both com1 and com2 are used. lcd s1~s43 output segment output segment output for driving lcd lcd s46(dsp1) s44(dsp2) output input segment output dsp input segment output for driving lcd (display input pins) lcd display input s47(ari) s45(ali) output input segment output analog input segment output for driving lcd (analog input pins) lcd analog input s48 (dspout) output segment output dsp output segment output for driving lcd (dsp output pins) lcd s49~s53 (arlo1~5) output segment output analog output segment output for driving lcd (analog output pins) lcd osc input oscillator input for clock generator resistor, capacitor ce input chip enable ce = high r chip enable status controller ck input data shift clock clock pulse input for the 1bit serial shift register. the data is shifted to 56 bit shift register at the rising edge of the clock. controller di input data input display data input controller inh input display blinking display blinking input (inh = low) controller maximum absolute limit (ta=25 o c , vss=0v) characteristic symbol value applicable pin unit maximum supply voltage v ddmax -0.3 ~ +7.0 v dd v v lcd max -0.3 ~ v dd +0.3 v lcd v input voltage v in1 -0.3 ~ v dd +0.3 ce, ck, di, inh v v in2 -0.3 ~ v dd +0.3 s44 ~ s47 output off(used as ari, ali dsp1, dsp2) v v in3 -0.3 ~ v dd +0.3 osc, output off v output voltage v o -0.3 ~ v dd +0.3 osc, output off v output current i o1 100 s1 ~ s53 m a i o2 1.0 com1, com2 ma allowable power dissipation p dmax 100 ta=85 o c mw operating temperature t opr -30 ~ +85 - o c storage temperature t stg -40 ~ +125 - o c
KS0035 53 segment static driver electrical characteristics dc characteristics (v dd =2.7v ~ 6,5v, v ss =0v, v lcd =2.7v ~ v dd , t a = - 30 ~ + 85 o c ) characteristics symbol test conditions min typ max unit operating voltage v dd - 2.7 - 6.5 driver supply voltage v lcd - 2.7 - v dd input ? high? voltage v ih1 ce, ck, di, inh 0.8v dd - v dd v input ? low ? voltage 1 v il1 0 - 0.2v dd input ? high ? voltage 2 v ih2 s44, s46 0.8v dd - v dd input ? low ? voltage 2 v il2 output off(used input pin dsp1, dsp2) 0 - 0.2v dd input ? high ? current 1 i ih1 ce, ck, di, inh(v i =v dd ) - - 5.0 input ? low ? current 1 i il1 ce, ck, di, inh(v i =0v) - - 5.0 m a input ? high ? current 2 i ih2 s44, s45, s46, s47(v i =v dd ) - - 10.0 input ? low ? current 2 i il2 s44, s45, s46, s47(v i =0v) - - 10.0 output ? high ? voltage 1 v oh1 s1 ~ s53(v lcd =3v, i o =-10 m a ) v lcd -0.5 - - output ? low ? voltage 1 v ol1 s1 ~ s53(v lcd =3v, i o =+10 m a ) - - 0.5 output ? high ? voltage 2 v oh2 com1, com2(v lcd =3v, i o =-100 m a ) v lcd -0.6 - - output ? low ? voltage 2 v ol2 com1, com2(v lcd =3v, i o = +100 m a ) - - 0.6 medium voltage v m1 com1, com2(v lcd =6.5v, i o = + 100 m a ) 2.65 3.25 3.85 v m2 com1, com2(v lcd =3.0v, i o = + 100 m a ) 0.9 1.5 2.1 first step lighting voltage v a1 s45, s47 0.07v dd 0.1v dd 0.13v dd v second step lighting voltage v a2 s45, s47 0.17v dd 0.2v dd 0.23v dd third step lighting voltage v a3 s45, s47 0.27v dd 0.3v dd 0.33v dd fourth step lighting voltage v a4 s45, s47 0.37v dd 0.4v dd 0.43v dd fifth step lighting voltage v a5 s45, s47 0.47v dd 0.5v dd 0.53v dd step voltage difference v step s45, s47 ( refer to fig. 2 ) 0.09v dd 0.1v dd 0.11v dd oscillation frequency f osc osc(r=51k w , c=680pf) 40 50 60 khz operating current i dd1 v dd =3v f ck =2mhz - 0.2 0.4 i dd2 v dd =6.5v r=51k w - 0.4 0.8 ma driving current i lcd1 v lcd =3v c=680pf - 0.6 1 i lcd2 v lcd =6.5v - 1.2 2
KS0035 53 segment static driver ac characteristics (v ss =0v, v dd =2.7v~ 6.5v, v lcd =2.7v ~ v dd , ta= - 30 ~ + 85 o c ) characteristic symbol test conditions min typ max unit clock pulse width t wckh v dd =5.0v 0.25 - - t wckl v dd =5.0v 0.25 - - data set-up time t su v dd =5.0v 0.25 - - data hold time t dh v dd =5.0v 0.25 - - m s 1/1 duty t 1 v dd =5.0v, at ce rising ce-di time 1/2 duty t 11 v dd =5.0v, at ce rising 1.0 - - t 12 v dd =5.0v, at di falling 1/1 duty t 2 v dd =5.0v, at ck rising ce-ck time 1/2 duty t 21 v dd =5.0v, at ck rising 1.25 - - t 22 v dd =5.0v, at ck rising ce disable time 1/2 duty t 3 v dd =5.0v, at ce falling 4.0 - - timing characteristics -. 1/1 duty(56 bits) -. 1/2 duty(112 bits) ce ck di t wckh t wckl t 1 t su t dh t su t dh t 2 d1 d2 dq dr ce ck di d1 t 11 t su t dh dr t su t dh d54 dr t 12 t 21 t 3 t 22 t wckh fig. 1. ac characteristics
KS0035 53 segment static driver output waveform - . 1 / 1duty f osc / 512 (hz ) com1 s1 ~ s53 unlighting time lighting time v lcd 0v v lcd 0v - . 1 / 2 duty com1 com2 f osc / 512 (hz) s1~ s52 output for segment when com1 side is lighted. s1 ~ s52 output for segment when com2 side is lighted. s1 ~ s52 output for segment when com1 & com2 sides are lighted. s1 ~ s52 output for segment when com1 & com2 sides are unlighted. v lcd 1 / 2 v lcd 0v v lcd 1 / 2 v lcd 0v v lcd 0v 0v v lcd v lcd v lcd 0v 0v
KS0035 53 segment static driver block function clock generator the oscillator is operated by connecting external resistor and capacitor. the clock of oscillator block is used as signal of common and segment driver. function decoder function decoder generates, using chip enable ( ce ), data ( di ), clock ( ck ) from controller, a signal which controls the function and mode of chip. for example ad / dsp function , drive mode, latch clock select and so forth. dp : drive mode select bit r 1 / 1 duty at ? 0? , 1 / 2 duty at ? dq : ad / dsp function select bit r segment output at ? 0 ?. ad / dsp function at ? dr : latch clock select bit r latch1 clock at ? 0 ? , latch 2 clock at ? note ) if ad / dsp function selected are not in use, ari, ali, dsp1, dsp2 pins are connected to vdd or vss in order to protect floating. dp dq dr data transfer ( 56 bits ) d1 d2 d3 d4 d5 d6 d7 d8 d47 d48 d49 d50 d51 d52 d53
KS0035 53 segment static driver shift register shift register consists of 53 data bits for display and 3 bits for function / mode select. data transfer mode . 1 / 1 duty data transfer ( 56 bits ) . 1 / 2 duty data transfer ( 112 bits ) - . d1 ~ d53 : display data ( 1 / 1 duty ) ? lighted at ? 1 - . d1 ~ d106 : display data ( 1 / 2 duty) ? unlighted at ? 0 note ) if ad / dsp functions are selected - . 1 / 1 duty : d46 ~ d53 r dummy bit (don?t care - . 1 / 2 duty : d88 ~ d106 r dummy bit (don?t care the example of data transfer d1 d2 d3 d4 d5 d6 d7 d8 d47 d48 d49 d50 d51 d52 d53 dp dq dr d54 d55 d56 d57 d58 d59 d60 d61 d102 d103 d104 d105 d106 d62 x x 1 * d53, d106 : dummy bit (do not care ) * x : don't care d54 d102 . 1 / 1 duty d1 d2 d3 d52 d53 0 dq 0 .under 52 segments at 1 / 2 duty d1 d2 d3 d52 d53 1 dq 0 .over 52 segments at 1 / 2 duty d1 d2 d3 d52 d53 1 dq 0 d54 d55 d56 d105 d106 x x 1 .under 52 segments at 1 / 2 duty , data can not be transferred as below figure. d54 d55 d56 d105 d106 x x 1 d1 d2 d3 d4 d5 d6 d7 d8 d47 d48 d49 d50 d51 d52 d53 dp dq dr
KS0035 53 segment static driver adc ( analog to digital converter ) adc consists of two analog inputs ( ari , ali ) and two adcs for level meter, and converts a analog input to 5 - level digital data in order to drive level meter. fig. 2. step voltage difference input voltage on s45 ( ali ) , s47( ari ) common driver latch and segment driver . latch has two signal, latch 1 clock latches d1 to d52 in 1/1 duty mode or 1/2 duty mode. latch 2 clock latches d54 to d105 in 1 / 2 duty mode d53 and d106 mean dummy bits ( don ? t care ) at 1 / 2 duty mode . if ad / dsp function is selected, s44 to s47 are input pins, s48 to s53 are output pins. 0.5v dd 0.4v dd 0.3v dd 0.2v dd 0.1v dd v step v step v step v step v step . 1 / 1 duty . 1 / 2 duty com1 v lcd 0v v lcd 0v 1/2v lcd v lcd 1/2v lcd 0v com1 com2 f osc / 512(hz)
KS0035 53 segment static driver correspondence between transfer ( external input ) data and output pin note : in the case of 1 / 1duty, only com1 is used. 0 1 0 1 com1 com2 s1 d1 d1 d1 d1 ? d2 d2 ? s2 d2 d2 d3 d3 ? d4 d4 ? s3 d3 d3 d5 d5 ? d6 d6 ? s26 d26 d26 d51 d51 ? d52 d52 ? s27 d27 d27 d54 d54 ? d55 d55 ? s28 d28 d28 d56 d56 ? d57 d57 ? s43 d43 d43 d86 d86 ? d87 d87 ? s44 d44 d44 d88 * dsp2 ? d89 ? s45 d45 d45 d90 *ali ? d91 ? s46 d46 *dsp1 d92 *dsp1 ? d93 ? s47 d47 *ari d94 *ari ? d95 ? s48 d48 *dspo1 d96 *dspo1 ? d97 *dspo2 ? s49 d49 *aro1 d98 *aro1 ? d99 *alo1 ? s50 d50 *aro2 d100 *aro2 ? d101 *alo2 ? s51 d51 *aro3 d102 *aro3 ? d103 *alo3 ? s52 d52 *aro4 d104 *aro4 ? d105 *alo4 ? s53 d53 *aro5 always lighting *aro5 ? always lighting *alo5 ? *note : 1 dp 0 1/2 duty dq 1/1 duty output dsp1, dsp2 : external display input data dspo1, dspo2 : external display output data ari , ali : ad converter input data aro1 to 5, alo1 to 5 : ad converter output data.
KS0035 53 segment static driver application circuit application circuit 1 application circuit 2 from controller v dd v lcd 680pf 51k w r 0.1 m f c + - inh osc v dd v lcd v ss ce ck di KS0035 680pf 51k w 0.1 m f from controller + - osc inh ce ck di KS0035 v dd v dd v lcd v ss

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